|Description:||Transfer fr .7:fr .5 into FSR .7:FSR .5|
|Operation:||FSR = &( fr ) & 0xE0|
|Details:||SX Users Manual page # 74|
|Microchip PIC syntax:|
The three literal bits of n are loaded into the bank-select bits (the high three bits) in the FSR register. See: SX18/20/28AC and SX18/20/28AC75 Addressing Modes and FSR Register
In PIC16C54 compatible mode, only one bank is enabled and the three high bits in FSR are always set. (INCFSZ FSR still skips when FSR is initially 0FFh even though the result is 0E0h.)
On the SX 48/52, the BANK instruction only selects one of 8 banks in either the lower 8 or upper 8 banks. FSR.7 selects the lower or upper group of 8 banks. To select a bank, use MOV FSR, #literal or add an SETB FSR.7 instruction after the BANK instruction." See: SX48/52BD Addressing Modes and FSR Register
Note: the first engineering releases of the SX48/52 chips behaved differently: BANK affected bits 5,6 and 7 and bit 4 had to be set manually.
PAGE and BANK cause an unusual operation when preceded by a skip instruction such as BTFSS and INCFSZ. Both the PAGE or BANK instruction and the following instruction are skipped, and the operation takes 3 cycles. This is designed to handle the case of reference to registers in other banks which must be coded as a bank then a register reference. The skip will skip both the bank and the register reference instuctions. See Skip for more details. If the following instruction happens to be another PAGE or BANK then it is also skipped along with the next instruction, and the operation takes 4 cycles. Any number of PAGE and BANK instructions can be skipped in this manner. Interrupts don't interfere with this operation.
|file: /Techref/scenix/inst/bank.htm, 3KB, , updated: 2005/4/22 11:55, local time: 2022/11/27 05:16,
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<A HREF="http://www.massmind.org/Techref/scenix/inst/bank.htm"> SX Embedded Controller Instruction - BANK fr</A>
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