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Scenix Lib IO OSI2 IR IR2SER

CC1B  Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 1

ADDR CODE  LINE SOURCE

           0001 
           0002 ; CC1B Ver 0.5B beta, Copyright (c) B Knudsen Data
           0003 ; C compiler for the Ubicom SX family
           0004 ; ************  25. Oct 2002  17:31  *************
           0005 
           0006         device SX28
           0007 
     0000  0008 INDF        EQU   $00
     0001  0009 TMR0        EQU   $01
     0004  0010 FSR         EQU   $04
     0005  0011 PORTA       EQU   $05
     0006  0012 PORTB       EQU   $06
     0000  0013 Carry       EQU   0
     0002  0014 Zero_       EQU   2
     0007  0015 PA2         EQU   7
     0005  0016 RA          EQU   $05
     0001  0017 IR_input    EQU   1
     0002  0018 RxD_pin     EQU   2
     0003  0019 _TxOUT      EQU   3
     0004  0020 LED         EQU   4
     000D  0021 x           EQU   $0D
     000E  0022 y           EQU   $0E
     0010  0023 r           EQU   $10
     0014  0024 med         EQU   $14
     0015  0025 min         EQU   $15
     0016  0026 max         EQU   $16
     0017  0027 rxBuf       EQU   $17
     0008  0028 in          EQU   $08
     0009  0029 Hex         EQU   $09
     000C  0030 timeout     EQU   $0C
     000A  0031 txBuf       EQU   $0A
     000B  0032 idx         EQU   $0B
     000F  0033 idx_2       EQU   $0F
           0034 
           0035   ; FILE ir2ser.c
           0036                         ;/*
           0037                         ; * IR reception
           0038                         ; * 05/Sep/1999 JLS & CAE
           0039                         ; * jls at certi.ufsc.br
           0040                         ; * cae at certi.ufsc.br
           0041                         ; * CC5xFree v3.0E (http://www.bknd.com)
           0042                         ; * use CC1B for SX
           0043                         ; */
           0044                         ;
           0045                         ;/*
           0046                         ;  Sony Data format: 12 bits
           0047                         ;
           0048                         ;  Bit zero:
           0049                         ;
           0050                         ;  400
           0051                         ;  +--+   +...
           0052                         ;  |  |   |
           0053                         ;  +  +---+
           0054                         ;      800
           0055                         ;
           0056                         ;  Bit one:
           0057                         ;
           0058                         ;  400
           0059                         ;  +--+      +...
           0060                         ;  |  |      |
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 2

ADDR CODE  LINE SOURCE

           0061                         ;  +  +------+
           0062                         ;       1400
           0063                         ;
           0064                         ;  Frame:
           0065                         ;               400    400
           0066                         ;  --+          +--+   +--+      +--+
           0067                         ;    |          |  |   |  |      |  |
           0068                         ;    +---2600---+  +---+  +------+  +...
           0069                         ;                   800     1400
           0070                         ;
           0071                         ;  Decoding algorithm:
           0072                         ;  - Detect 2600us pulse,
           0073                         ;  - measure next high pulse as P1 (400us)
           0074                         ;  - measure next low  pulse as P2 (800/1400us)
           0075                         ;  - store min(P1)
           0076                         ;  - store max(P2)
           0077                         ;  After all measurements:
           0078                         ;  - calculate mean = (max-min)/2 + min
           0079                         ;  - For all (P1,P2) measured:
           0080                         ;    . Add P1+P2=P3
           0081                         ;    . If P3< mean => bit is zero
           0082                         ;    . If P3>=mean => bit is one
           0083                         ;
           0084                         ;  Measures with Timer0 & Prescaler:16
           0085                         ;    2600us = 162
           0086                         ;    1400us = 87
           0087                         ;     800us = 50
           0088                         ;     400us = 25
           0089                         ;
           0090                         ;     400+800  = 25+50 = 75
           0091                         ;     400+1400 = 25+87 = 112
           0092                         ;     mean ~= (112-75)/2+75 = 18+75 = 93
           0093                         ;*/
           0094                         ;
           0095                         ;#define         _sx28_
           0096                         ;#include        <sx28.h>
           0097                         ;
           0098                         ;#ifdef _12C508_
           0099                         ;        bit     _TxOUT          @ GP0;
           0100                         ;        bit     RxD_pin         @ GP1;
           0101                         ;        bit     IR_input        @ GP2;
           0102                         ;#else
           0103                         ;        #define RP0             STATUS.5
           0104                         ;        #pragma update_RP 0   /* OFF */
           0105                         ;        #define DEF_TRISA       0
           0106                         ;        #define DEF_TRISB       6
           0107                         ;        bit     Rele            @ PORTA.1;
           0108                         ;
           0109                         ;        bit     IR_input        @ PORTB.1;
           0110                         ;        bit     RxD_pin         @ PORTB.2;
           0111                         ;        bit     _TxOUT          @ PORTB.3;
           0112                         ;        bit     LED             @ PORTB.4;
           0113                         ;#endif
           0114                         ;
           0115                         ;
           0116                         ;
           0117                         ;#ifdef _sx28_
           0118                         ;	unsigned char x,y;
           0119                         ;bank0	unsigned char r[4];
           0120                         ;bank0	unsigned char med,min,max,rxBuf;
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 3

ADDR CODE  LINE SOURCE

           0121                         ;bank1	unsigned char buff[16];
           0122                         ;bank2	unsigned char buff2[16];
           0123                         ;#else
           0124                         ;	unsigned char x,y,med,min,max,rxBuf;
           0125                         ;	unsigned char r[4];
           0126                         ;	unsigned char buff[16];
           0127                         ;	unsigned char buff2[16];
           0128                         ;	#endif
           0129                         ;
           0130                         ;void TxSerial (unsigned char txBuf);
           0131                         ;
           0132                         ;/*--------------------------------------------------------------------------
                   */
           0133                         ;void TxEnter (void) {
           0134 TxEnter
           0135                         ;/*--------------------------------------------------------------------------
                   */
           0136                         ;        TxSerial(0xD);
0000 0C0D  0137         MOV   W,#13
0001 0928  0138         CALL  TxSerial
           0139                         ;        TxSerial(0xA);
0002 0C0A  0140         MOV   W,#10
0003 0A28  0141         JMP   TxSerial
           0142                         ;}
           0143                         ;
           0144                         ;/*--------------------------------------------------------------------------
                   */
           0145                         ;void TxHexAscii (unsigned char in) {
           0146 TxHexAscii
0004 0028  0147         MOV   in,W
           0148                         ;/*--------------------------------------------------------------------------
                   */
           0149                         ;        unsigned char Hex;
           0150                         ;
           0151                         ;        Hex = swap(in);                 // upper nibble
0005 0388  0152         MOV   W,<>in
0006 0029  0153         MOV   Hex,W
           0154                         ;        Hex &= 0x0F;
0007 0C0F  0155         MOV   W,#15
0008 0169  0156         AND   Hex,W
           0157                         ;        if (Hex<10) Hex += 0x30;
0009 0C0A  0158         MOV   W,#10
000A 0089  0159         MOV   W,Hex-W
000B 0603  0160         SNB   3.Carry
000C 0A10  0161         JMP   m001
000D 0C30  0162         MOV   W,#48
000E 01E9  0163         ADD   Hex,W
           0164                         ;        else Hex += 0x37;
000F 0A12  0165         JMP   m002
0010 0C37  0166 m001    MOV   W,#55
0011 01E9  0167         ADD   Hex,W
           0168                         ;        TxSerial(Hex);
0012 0209  0169 m002    MOV   W,Hex
0013 0928  0170         CALL  TxSerial
           0171                         ;        Hex = in & 0x0F;
0014 0C0F  0172         MOV   W,#15
0015 0148  0173         AND   W,in
0016 0029  0174         MOV   Hex,W
           0175                         ;        if (Hex<0x0A) Hex += 0x30;
0017 0C0A  0176         MOV   W,#10
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 4

ADDR CODE  LINE SOURCE

0018 0089  0177         MOV   W,Hex-W
0019 0603  0178         SNB   3.Carry
001A 0A1E  0179         JMP   m003
001B 0C30  0180         MOV   W,#48
001C 01E9  0181         ADD   Hex,W
           0182                         ;        else Hex += 0x37;
001D 0A20  0183         JMP   m004
001E 0C37  0184 m003    MOV   W,#55
001F 01E9  0185         ADD   Hex,W
           0186                         ;        TxSerial(Hex);
0020 0209  0187 m004    MOV   W,Hex
0021 0A28  0188         JMP   TxSerial
           0189                         ;}
           0190                         ;
           0191                         ;/*--------------------------------------------------------------------------
                   */
           0192                         ;void Delay_uSeg (unsigned char timeout) {
           0193 Delay_uSeg
0022 002C  0194         MOV   timeout,W
           0195                         ;/*--------------------------------------------------------------------------
                   */
           0196                         ;        // delay = 3*timeout + 7uS (including call and return)
           0197                         ;
           0198                         ;        while (1) {
           0199                         ;                timeout--;
0023 02EC  0200 m005    DECSZ timeout
           0201                         ;                if (timeout==0) {
0024 0A23  0202         JMP   m005
           0203                         ;                        nop();
0025 0000  0204         NOP  
           0205                         ;                        nop();
0026 0000  0206         NOP  
           0207                         ;                        return;
0027 000C  0208         RET  
           0209                         ;                }
           0210                         ;        }
           0211                         ;}
           0212                         ;
           0213                         ;/*--------------------------------------------------------------------------
                   */
           0214                         ;void TxSerial (unsigned char txBuf) {
           0215 TxSerial
0028 002A  0216         MOV   txBuf,W
           0217                         ;/*--------------------------------------------------------------------------
                   */
           0218                         ;
           0219                         ;/*
           0220                         ; ;--------------------------------------------------------------------------
                   -*
           0221                         ; ; Transmit 1 start bit Lo, 8 data bits and 1 stop bit Hi at 9600 bps
           0222                         ; ; No Parity
           0223                         ; ; Byte time = 1.040 mS
           0224                         ; ; Bit  time = 104 uS (0.16% erro w/4.00 Mhz Internal RC)
           0225                         ; ; Input : W = byte to be transmitted
           0226                         ; ; Output: byte transmitted by serial pin
           0227                         ; ;--------------------------------------------------------------------------
                   -*
           0228                         ;*/
           0229                         ;
           0230                         ;    char idx;
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 5

ADDR CODE  LINE SOURCE

           0231                         ;
           0232                         ;        while (1)
           0233                         ;        {
           0234                         ;                Carry = 0;                      // start bit
0029 0403  0235         CLRB  3.Carry
           0236                         ;                for (idx=10; idx; idx--)        // 3us
002A 0C0A  0237         MOV   W,#10
002B 002B  0238         MOV   idx,W
002C 022B  0239 m006    TEST  idx
002D 0643  0240         SNB   3.Zero_
002E 0A3A  0241         JMP   m007
           0242                         ;                {
           0243                         ;                        _TxOUT = Carry;         // 4us
002F 0703  0244         SB    3.Carry
0030 0466  0245         CLRB  6._TxOUT
0031 0603  0246         SNB   3.Carry
0032 0566  0247         SETB  6._TxOUT
           0248                         ;                        Delay_uSeg(28);         // 91us (28*3+7)
0033 0C1C  0249         MOV   W,#28
0034 0922  0250         CALL  Delay_uSeg
           0251                         ;                        Carry  = 1;             // 1us
0035 0503  0252         SETB  3.Carry
           0253                         ;                        txBuf  = rr(txBuf);     // 1us
0036 032A  0254         RR    txBuf
           0255                         ;                        nop();                  // 1us
0037 0000  0256         NOP  
           0257                         ;                }                               // 3us
0038 00EB  0258         DEC   idx
0039 0A2C  0259         JMP   m006
           0260                         ;                return;
003A 000C  0261 m007    RET  
           0262                         ;        }
           0263                         ;}
           0264                         ;
           0265                         ;/*--------------------------------------------------------------------------
                   */
           0266                         ;void RxSerial (void) {
           0267 RxSerial
           0268                         ;/*--------------------------------------------------------------------------
                   */
           0269                         ;
           0270                         ;/*
           0271                         ; ;--------------------------------------------------------------------------
                   -*
           0272                         ; ; Receives 1 start bit Lo, 8 data bits and 1 stop bit Hi at 9600 bps
           0273                         ; ; No Parity
           0274                         ; ; Byte time = 1.040 mS
           0275                         ; ; Bit  time = 104 uS (0.16% erro w/4.00 Mhz Internal RC)
           0276                         ; ;
           0277                         ; ; False start bit check
           0278                         ; ;
           0279                         ; ; Start bit hunting timeout = 4*1.283ms
           0280                         ; ;
           0281                         ; ; Input  : none
           0282                         ; ; Output : Carry = 1 => success
           0283                         ; ;          rxBuf = input byte
           0284                         ; ;          Carry = 0 => error (timeout or stop bit=0)
           0285                         ; ;--------------------------------------------------------------------------
                   -*
           0286                         ;*/
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 6

ADDR CODE  LINE SOURCE

           0287                         ;        char idx;
           0288                         ;
           0289                         ;        rxBuf = 4;                              // 5.135 ms timeout
003B 0C04  0290         MOV   W,#4
003C 0064  0291         CLR   FSR
003D 0037  0292         MOV   rxBuf,W
           0293                         ;        idx   = 0;
003E 006F  0294         CLR   idx_2
           0295                         ;
           0296                         ;        while (1)
           0297                         ;        {
           0298                         ;                while (RxD_pin)                 // input "high"
003F 0746  0299 m008    SB    6.RxD_pin
0040 0A47  0300         JMP   m009
           0301                         ;                {
           0302                         ;                        if ((-- idx)==0)
0041 02EF  0303         DECSZ idx_2
0042 0A3F  0304         JMP   m008
           0305                         ;                        {
           0306                         ;                                if ((-- rxBuf)==0)
0043 02F7  0307         DECSZ rxBuf
0044 0A3F  0308         JMP   m008
           0309                         ;                                {
           0310                         ;                                        Carry = 0;
0045 0403  0311         CLRB  3.Carry
           0312                         ;                                        return;
0046 000C  0313         RET  
           0314                         ;                                }
           0315                         ;                        }
           0316                         ;                }
           0317                         ;
           0318                         ;                Delay_uSeg(14);                 // 1/2 bit delay (14*3+7)
0047 0C0E  0319 m009    MOV   W,#14
0048 0922  0320         CALL  Delay_uSeg
           0321                         ;                if (RxD_pin)
0049 0646  0322         SNB   6.RxD_pin
           0323                         ;                        continue;               // false start bit detection
                   
004A 0A3F  0324         JMP   m008
           0325                         ;
           0326                         ;                rxBuf = 0x80;                   // 8 bits counter and recept
                   ion buffer
004B 0C80  0327         MOV   W,#128
004C 0037  0328         MOV   rxBuf,W
           0329                         ;                nop();
004D 0000  0330         NOP  
           0331                         ;                nop();                          // timming adjustment
004E 0000  0332         NOP  
           0333                         ;
           0334                         ;                do
           0335                         ;                {
           0336                         ;                        Delay_uSeg(30);         // (30*3+7)us
004F 0C1E  0337 m010    MOV   W,#30
0050 0922  0338         CALL  Delay_uSeg
           0339                         ;                        Carry = RxD_pin;        // bit read
0051 0403  0340         CLRB  3.Carry
0052 0646  0341         SNB   6.RxD_pin
0053 0503  0342         SETB  3.Carry
           0343                         ;                        rxBuf = rr(rxBuf);      // store and count
0054 0337  0344         RR    rxBuf
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 7

ADDR CODE  LINE SOURCE

           0345                         ;                }
           0346                         ;                while (Carry==0);
0055 0703  0347         SB    3.Carry
0056 0A4F  0348         JMP   m010
           0349                         ;                Delay_uSeg(30);                 // 1 bit delay
0057 0C1E  0350         MOV   W,#30
0058 0922  0351         CALL  Delay_uSeg
           0352                         ;                nop();                          // timming adjustment
0059 0000  0353         NOP  
           0354                         ;                Carry = RxD_pin;                // stop bit read
005A 0403  0355         CLRB  3.Carry
005B 0646  0356         SNB   6.RxD_pin
005C 0503  0357         SETB  3.Carry
           0358                         ;                return;                         // 100 us availiable
005D 000C  0359         RET  
           0360                         ;        }
           0361                         ;}
           0362                         ;
           0363                         ;
           0364                         ;/*--------------------------------------------------------------------------
                   */
           0365                         ;void main (void) {
           0366 main
           0367                         ;/*--------------------------------------------------------------------------
                   */
           0368                         ;
           0369                         ;#ifdef _12C508_
           0370                         ;//      OSCCAL  = W;                                    // OscCal Value - OT
                   P part
           0371                         ;        OSCCAL  = 0xB0;                                 // OscCal Value - Wi
                   ndowed part
           0372                         ;        GPIO    = 0x00;
           0373                         ;        TRIS    = 0x08;                                 // GP3 input
           0374                         ;	#endif
           0375                         ;
           0376                         ;#ifdef _sx28_
           0377                         ;    #pragma config &= 0b11010011 // reg 1 = RTCC, no int on RTCC, RTCC inter
                   nal, prescale, 1:16
           0378                         ;      PORTA   = 0;
005E 0065  0379         CLR   PORTA
           0380                         ;      PORTB   = 0;
005F 0066  0381         CLR   PORTB
           0382                         ;      DDRA = DEF_TRISA;
0060 005F  0383         MOV   M,#15
0061 0C00  0384         MOV   W,#0
0062 0005  0385         MOV   !RA,W
           0386                         ;      DDRA = DEF_TRISB;
0063 0C06  0387         MOV   W,#6
0064 0005  0388         MOV   !RA,W
           0389                         ;	PA0 = 0;
           0390                         ;	PA1 = 0;
           0391                         ;	PA2 = 0;
0065 04E3  0392         CLRB  3.PA2
           0393                         ;	#endif
           0394                         ;
           0395                         ;#ifdef _16f84_
           0396                         ;        INTCON  = 0;                                    // no interrupts
           0397                         ;        PCLATH  = 0;                                    // bank 0
           0398                         ;        PORTA   = 0;
           0399                         ;        PORTB   = 0;
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 8

ADDR CODE  LINE SOURCE

           0400                         ;        TRISA   = DEF_TRISA;
           0401                         ;        TRISB   = DEF_TRISB;
           0402                         ;        RP0     = 1;                                    // RAM bank 1
           0403                         ;        RP0     = 0;                                    // RAM bank 0
           0404                         ;	#endif
           0405                         ;
           0406                         ;        while (1)
           0407                         ;        {
           0408                         ;                /* set vars to start */
           0409                         ;                min  = 255;                             // min period
0066 0064  0410         CLR   FSR
0067 0CFF  0411 m011    MOV   W,#255
0068 0035  0412         MOV   min,W
           0413                         ;                max  = 0;                               // max period
0069 0076  0414         CLR   max
           0415                         ;
           0416                         ;                y    = 0;                               // pointer to buffer
                   
006A 006E  0417         CLR   y
           0418                         ;                x    = 12;                              // only 12 bits
006B 0C0C  0419         MOV   W,#12
006C 002D  0420         MOV   x,W
           0421                         ;
           0422                         ;                /* start bit management */
           0423                         ;                while (IR_input==1);                    // wait for 0
006D 0626  0424 m012    SNB   6.IR_input
006E 0A6D  0425         JMP   m012
           0426                         ;
           0427                         ;                /* 2600us start bit */
           0428                         ;                while (IR_input==0);                    // wait for 1
006F 0726  0429 m013    SB    6.IR_input
0070 0A6F  0430         JMP   m013
           0431                         ;
           0432                         ;                TMR0 = 0;                               // start counter
0071 0061  0433         CLR   TMR0
           0434                         ;                do
           0435                         ;                {
           0436                         ;//                        buff[y] = 0; 
           0437                         ;//                        buff2[y] = 0; 
           0438                         ;                        /* measure high pulse */
           0439                         ;                        while (TMR0==0);                // wait TMR0 advance
                   
0072 0201  0440 m014    MOV   W,TMR0
0073 0643  0441         SNB   3.Zero_
0074 0A72  0442         JMP   m014
           0443                         ;                        while (IR_input==1)             // wait for 0
0075 0726  0444 m015    SB    6.IR_input
0076 0A7B  0445         JMP   m016
           0446                         ;                        {
           0447                         ;                                if (TMR0==0)            // timer overflow (4
                   096us) ?
0077 0201  0448         MOV   W,TMR0
0078 0743  0449         SB    3.Zero_
0079 0A75  0450         JMP   m015
           0451                         ;	goto	frame_end	; // yes, exit
007A 0AA1  0452         JMP   m021
           0453                         ;                        }
           0454                         ;                        buff[y] = TMR0;                 // store period
007B 0C30  0455 m016    MOV   W,#48
007C 01CE  0456         ADD   W,y
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 9

ADDR CODE  LINE SOURCE

007D 0024  0457         MOV   FSR,W
007E 0201  0458         MOV   W,TMR0
007F 0020  0459         MOV   INDF,W
           0460                         ;                        med = TMR0;                     // save high period
0080 0201  0461         MOV   W,TMR0
0081 0018  0462         BANK  0
0082 0034  0463         MOV   med,W
           0464                         ;                        TMR0 = 0;                       // start counter
0083 0061  0465         CLR   TMR0
           0466                         ;
           0467                         ;                        /* measure low pulse */
           0468                         ;
           0469                         ;                        while (TMR0==0);                // wait TMR0 advance
                   
0084 0201  0470 m017    MOV   W,TMR0
0085 0643  0471         SNB   3.Zero_
0086 0A84  0472         JMP   m017
           0473                         ;                        while (IR_input==0);            // wait for 1
0087 0726  0474 m018    SB    6.IR_input
0088 0A87  0475         JMP   m018
           0476                         ;                        buff2[y] = TMR0;                // store period
0089 0C50  0477         MOV   W,#80
008A 01CE  0478         ADD   W,y
008B 0024  0479         MOV   FSR,W
008C 0201  0480         MOV   W,TMR0
008D 0020  0481         MOV   INDF,W
           0482                         ;                        med += TMR0;                    // total period
008E 0201  0483         MOV   W,TMR0
008F 0018  0484         BANK  0
0090 01F4  0485         ADD   med,W
           0486                         ;                        TMR0 = 0;                       // start counter
0091 0061  0487         CLR   TMR0
           0488                         ;                        if (med>=max) max = med;        // find max
0092 0216  0489         MOV   W,max
0093 0094  0490         MOV   W,med-W
0094 0703  0491         SB    3.Carry
0095 0A98  0492         JMP   m019
0096 0214  0493         MOV   W,med
0097 0036  0494         MOV   max,W
           0495                         ;                        if (med<min)  min = med;        // find min
0098 0215  0496 m019    MOV   W,min
0099 0094  0497         MOV   W,med-W
009A 0603  0498         SNB   3.Carry
009B 0A9E  0499         JMP   m020
009C 0214  0500         MOV   W,med
009D 0035  0501         MOV   min,W
           0502                         ;
           0503                         ;                        y++;                            // bump pointer
009E 02AE  0504 m020    INC   y
           0505                         ;                        x--;                            // dec max bits
009F 02ED  0506         DECSZ x
           0507                         ;                }
           0508                         ;                while (x);
00A0 0A72  0509         JMP   m014
           0510                         ;frame_end:
           0511                         ;                LED = 1;
00A1 0586  0512 m021    SETB  6.LED
           0513                         ;                med  = max - min;
00A2 0215  0514         MOV   W,min
00A3 0096  0515         MOV   W,max-W
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 10

ADDR CODE  LINE SOURCE

00A4 0034  0516         MOV   med,W
           0517                         ;                med /= 2;
00A5 0403  0518         CLRB  3.Carry
00A6 0334  0519         RR    med
           0520                         ;                med += min;
00A7 0215  0521         MOV   W,min
00A8 01F4  0522         ADD   med,W
           0523                         ;
           0524                         ;                r[0] = 0;
00A9 0070  0525         CLR   r
           0526                         ;                r[1] = 0;
00AA 0071  0527         CLR   r+1
           0528                         ;                r[2] = 0;
00AB 0072  0529         CLR   r+2
           0530                         ;                r[3] = 0;
00AC 0073  0531         CLR   r+3
           0532                         ;
           0533                         ;                x = y;	//save the size
00AD 020E  0534         MOV   W,y
00AE 002D  0535         MOV   x,W
           0536                         ;                do
           0537                         ;                {
           0538                         ;                        Carry = 0;
00AF 0403  0539 m022    CLRB  3.Carry
           0540                         ;                        r[3] = rl(r[3]);
00B0 0373  0541         RL    r+3
           0542                         ;                        r[2] = rl(r[2]);
00B1 0372  0543         RL    r+2
           0544                         ;                        r[1] = rl(r[1]);
00B2 0371  0545         RL    r+1
           0546                         ;                        r[0] = rl(r[0]);
00B3 0370  0547         RL    r
           0548                         ;                        y--;
00B4 00EE  0549         DEC   y
           0550                         ;                        max = buff[y];
00B5 0C30  0551         MOV   W,#48
00B6 01CE  0552         ADD   W,y
00B7 0024  0553         MOV   FSR,W
00B8 0200  0554         MOV   W,INDF
00B9 0018  0555         BANK  0
00BA 0036  0556         MOV   max,W
           0557                         ;                        max += buff2[y];
00BB 0C50  0558         MOV   W,#80
00BC 01CE  0559         ADD   W,y
00BD 0024  0560         MOV   FSR,W
00BE 0200  0561         MOV   W,INDF
00BF 0018  0562         BANK  0
00C0 01F6  0563         ADD   max,W
           0564                         ;                        if (max>=med) r[3]++;
00C1 0214  0565         MOV   W,med
00C2 0096  0566         MOV   W,max-W
00C3 0603  0567         SNB   3.Carry
00C4 02B3  0568         INC   r+3
           0569                         ;                } while (y);
00C5 022E  0570         TEST  y
00C6 0743  0571         SB    3.Zero_
00C7 0AAF  0572         JMP   m022
           0573                         ;
           0574                         ;                /* now r[0],r[1],r[2], r[3] has the frame */
           0575                         ;                /* Tx the periods and the encoded word */
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 11

ADDR CODE  LINE SOURCE

           0576                         ;
           0577                         ;                TxHexAscii(x*2);	//size
00C8 0403  0578         CLRB  3.Carry
00C9 034D  0579         MOV   W,<<x
00CA 0904  0580         CALL  TxHexAscii
           0581                         ;                TxSerial(0x20);
00CB 0C20  0582         MOV   W,#32
00CC 0928  0583         CALL  TxSerial
           0584                         ;                TxHexAscii(med);
00CD 0214  0585         MOV   W,med
00CE 0904  0586         CALL  TxHexAscii
           0587                         ;                TxEnter();
00CF 0900  0588         CALL  TxEnter
           0589                         ;
           0590                         ;                for(y=0;y<x; y++) {
00D0 006E  0591         CLR   y
00D1 020D  0592 m023    MOV   W,x
00D2 008E  0593         MOV   W,y-W
00D3 0603  0594         SNB   3.Carry
00D4 0AE4  0595         JMP   m024
           0596                         ;                        TxHexAscii(buff[y]);
00D5 0C30  0597         MOV   W,#48
00D6 01CE  0598         ADD   W,y
00D7 0024  0599         MOV   FSR,W
00D8 0200  0600         MOV   W,INDF
00D9 0904  0601         CALL  TxHexAscii
           0602                         ;                        TxHexAscii(buff2[y]);
00DA 0C50  0603         MOV   W,#80
00DB 01CE  0604         ADD   W,y
00DC 0024  0605         MOV   FSR,W
00DD 0200  0606         MOV   W,INDF
00DE 0904  0607         CALL  TxHexAscii
           0608                         ;                        TxSerial(0x20);
00DF 0C20  0609         MOV   W,#32
00E0 0928  0610         CALL  TxSerial
           0611                         ;                        }
00E1 02AE  0612         INC   y
00E2 0018  0613         BANK  0
00E3 0AD1  0614         JMP   m023
           0615                         ;                TxEnter();
00E4 0900  0616 m024    CALL  TxEnter
           0617                         ;
           0618                         ;                TxHexAscii(r[0]);
00E5 0210  0619         MOV   W,r
00E6 0904  0620         CALL  TxHexAscii
           0621                         ;                TxHexAscii(r[1]);
00E7 0211  0622         MOV   W,r+1
00E8 0904  0623         CALL  TxHexAscii
           0624                         ;                TxHexAscii(r[2]);
00E9 0212  0625         MOV   W,r+2
00EA 0904  0626         CALL  TxHexAscii
           0627                         ;                TxHexAscii(r[3]);
00EB 0213  0628         MOV   W,r+3
00EC 0904  0629         CALL  TxHexAscii
           0630                         ;
           0631                         ;                TxEnter();
00ED 0900  0632         CALL  TxEnter
           0633                         ;                LED = 0;
00EE 0486  0634         CLRB  6.LED
           0635                         ;        }
CC1B Ver 0.5B beta,   File: ir2ser.c            25. Oct 2002  17:31   Page 12

ADDR CODE  LINE SOURCE

00EF 0A67  0636         JMP   m011
           0637 
     0000  0638         ORG $07FF
07FF 0A5E  0639         GOTO main
     0000  0640         END


file: /Techref/scenix/lib/io/osi2/ir/ir2ser.lst, 37KB, , updated: 2002/10/25 18:31, local time: 2020/10/21 00:43,
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