Scott Dattalo says:
But here's a quick tutorial (that overlooks many of the essential details...)
A PLL is fed a signal of unkown but banded frequency. The PLL measures the frequency indirectly by generating a separate waveform at the same frequency. The algorithm for generating this separate frequency is simple:
If the incoming frequency is higher than the one synthesized by the pll, then increase the frequency of the synthesized waveform other wise decrease it.
The difficult part of course is implementing this. How do you 'synthesize a waveform'? How do you increase or decrease its frequency? How do you compare two signals for differences in frequency?
These three questions are often answered in the classical PLL block diagram:IN +---------------+ |-------------+ +-----+ OUT ---> | phase compare | -> | Loop filter | -> | VCO | ----+--> | | |-------------+ +-----+ | +->| | | | +---------------+ | | | | | +------------------------------------------------------+
The frequency comparsion is performed in the first block. As its name suggests, the phase between the two signals is compared. This implies that the two signals are the same frequency. It just doesn't make sense to speak of the phase difference between two signals of differeing frequency. So why have a phase comparator? Well what you can do is compare phase on a per cycle basis between the two wave forms. For example, if the incoming signal is a sinewave that makes a zero crossing at t = t1 then the next zero crossing of the output wave form may be expressed in terms of a percentage of the period of the incoming wave form. The goal of the PLL is to get those zero crossings to align.
Skipping the Loop Filter for the moment, the VCO or Voltage Controlled Oscillator, produces a waveform whose frequency is directly proportional to a voltage. You double the voltage and the VCO will double its frequency. The response of the VCO, or the at which it responds to voltage changes, is a strong function of the requirements of your system. But typically, the control to the VCO is dithered around a DC voltage. This DC voltage is the one that causes the VCO to produce the frequency that matches the incoming signal. But why dither? Well, it's similar to the way an opamp works. An opamp has a positive and negative input. If the positive input is greater than the negative, then the opamp's output is driven high otherwise it's driven low. Without any feedback, the output would be driven towards one of the supply rails. With feedback, the output is driven to the voltage that minimizes (or attempts to minimize) the difference in voltages between the positive and negative inputs. The exact same thing (conceptually) happens here. The difference is that instead of voltages, frequencies (or more accurately, phases) are being compared. However, this frequency difference is translated into a (DC) voltage. But from a time point of view, frequency is changing and DC is constant - something's got to give.
Here's where the loop filter comes in. So far I've tried to be vary abstract and not say that the signals are sine waves or square waves or whatever. But it's convenient to imagine the phase comparator producing pulses (they don't all do this...). If the phase comparator's output is +1 then this may indicate that the incoming frequency is higher than the VCO's and consequently the DC control voltage to the VCO needs to be increased. If the phase comparator output is a 0 then the opposite case is true and the VCO needs to be decreased. But 0's and 1's need to be converted into a suitable DC control voltage for the VCO. Yhat's the job of the loop filter. In this example, you could say, "oh, that's easy - all you need is a low pass filter!" But in reality it depends on your VCO and on how you design the loop filter. The problem is that you have mixed constraints. You want the PLL to accurately lock onto a signal and you want the PLL also to respond to changes in the incoming frequency. The accuracy constraint means you'd like the changes in the VCO control voltage only slightly affect the VCO frequency. On the other hand, the response to a change in frequency constraint means you'd like the VCO to be sensitive to changes in the control voltage. This mixed constraint problem is what typically makes PLL's a challenge.
|file: /Techref/logic/dsp/plls.htm, 6KB, , updated: 2003/3/22 23:16, local time: 2023/9/27 11:24,
|©2023 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?|
<A HREF="http://www.massmind.org/techref/logic/dsp/plls.htm"> Digital Signal Processing Logic - Phase Locked Loops</A>
|Did you find what you needed?|
Welcome to massmind.org!
Welcome to www.massmind.org!