The OPTION register sets several device configuration options, mostly related to operation of the Real- Time Clock/ Counter. The format of the register is shown below. Upon reset, all bits in this register are set to 1.
|Bit 7||Bit 0|
Clear the RTW bit to 0 to make W available as a memory- mapped register at address 01h. Set the RTW bit to 1 for the default register configuration, with RTCC at address 01h. Before you can clear the RTW bit, the option must be enabled by programming the OPTIONX bit to 0 in the FUSE word in the program memory or in other words, include the device optionx directive in you source file.
Despite Parallax documentation to the contrairy, the RTCC counter continues to run when register 1 is showng W and switching between showing W and RTCC does not apparently have any affect on either register.
The great advantage of this option is that the W register can be manipulated just like any other file register!
Clear the RTE_ IE bit to 0 to enable the interrupt that occurs upon rollover of the RTCC counter, or set this bit to 1 to disable the interrupt. Before you can clear the RTE_ IE bit, the option must be enabled by programming the OPTIONX bit to 0 in the FUSE word in the program memory.
Clear the RTS bit to 0 to have the RTCC counter incremented automatically with each instruction cycle (or a specified number of instruction cycles). This mode can be used to implement a real- time clock. Set the RTS bit to 1 to have the RTCC counter incremented once each time a transition is detected on the RTCC input pin (or a specified number of transitions). This mode can be used as an external event counter.
When the RTCC counter is configured to count transitions received on the RTCC pin (when RTS= 1), the RTCC bit specifies the type of signal edges detected on the RTCC pin. Set RTE_ ES to 1 to detect high- to- low transitions on the RTCC pin. Clear RTE_ ES to 0 to detect low- to- high transitions on the RTCC pin.
Clear the PSA bit to 0 to have the internal prescaler operate with the Real- Time Clock/ Counter. In that case, the RTCC counter is incremented once every n instruction cycles, with the number n determined by the PS2: PS0 bits; and the Watchdog timer operates at the default rate.
Set the PSA bit to 1 to have the internal prescaler operate with the Watchdog timer. In that case, a Watchdog reset is generated after n timeouts of the Watchdog timer register, with the number n determined by the PS2: PS0 bits; and the RTCC register is incremented once per instruction cycle or external event.
Use this bit field in conjunction with the PSA bit to specify an operating rate for the RTCC timer or Watchdog timer that is lower than the default rate. Table 2- 6 shows the clock divide- by factors determined by these bits. Note that for a given setting, the divide- by factor depends on whether you use the prescaler register with the RTCC timer (PSA= 0) or with the Watchdog timer (PSA= 1). For the RTCC timer, the timer is incremented once every 2, 4, 8, ... or 256 instruction cycles or external events. For the Watchdog timer, a Watchdog reset is triggered after 1, 2, 4, ... or 128 overflows of the Watchdog timer register.
|PS2:PS0||RTCC Timer Input
Divide-By Factor (PSA=0)
|Watchdog Timer Outputs
Divide-By Factor (PSA=1)
|000||2||1 (timeout = 0.018 sec)|
|001||4||2 (timeout = 0.037 sec)|
|010||8||4 (timeout = 0.073 sec)|
|011||16||8 (timeout = 0.15 sec)|
|100||32||16 (timeout = 0.29 sec)|
|101||64||32 (timeout = 0.59 sec)|
|110||128||64 (timeout = 1.17 sec)|
|111||256||128 (timeout = 2.34 sec)|
|file: /Techref/scenix/inst/option.htm, 5KB, , updated: 1999/3/6 13:35, local time: 2022/1/18 23:40,
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<A HREF="http://www.massmind.org/techref/scenix/inst/option.htm"> OPTION (Device Option Register)</A>
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