|Description:||Skip next instruction word|
|Actually compiles to:||sb 2.0 /snb 2.0|
|Microchip PIC syntax:||BTFSC/BTFSS 2,0|
Actually compiles a sb 2.0 if at an odd address and a snb 2.0 if at an even address. Since register 2 is the PC, there will always be a 1 in the PC at an odd address and no 1 at an even address. There is no skip always instruction in the SX.
The SX has a built in trick which skips the next instruction after a page or bank instruction. This allows the user to skip long calls (page,call). It takes 3 cycles to skip these two instructions. It also means that if the user were just trying to skip the page, the SX would also skip the next instruction afterwards. It's a cool trick, but only once you know it's there. If you don't, it can be really frustrating to try to figure out the problem.
This trick has been built in to deal with doing bank instructions as well. It would skip the bank, and the next instruction after the bank. It makes skipping register operations extremely easy, but only once you know it is there. If you do not wish the instruction following the bank or page instruction to be skiped inserting a nop between the bank or page instruction and the next instruction would fix the problem.
Things really get interesting when there are several BANK and PAGE instructions in a row. Theyre ALL skipped, and a cycle is taken for each. Interrupts do not interfere with this skipping behavior. If a non bank or page instruction is skipped, a bank or page instruction following it will not be skipped. Test with the following:
page $700 clc snc setb temp.0 page 0 jmp $10 page $700 clc snc page 0 bank temp setb temp.0 jmp $10
JMP and SKIP instructions take 2 cycles in >compatible mode, not 4 as stated in Table 3-7 in User's manual page 53.
|file: /Techref/scenix/inst/skip.htm, 3KB, , updated: 2002/8/5 17:39, local time: 2023/3/31 03:31,
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<A HREF="http://www.massmind.org/techref/scenix/inst/skip.htm"> SX Embedded Controller Instruction </A>
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